Reference voltage generation circuit, data driver, display device, and electronic instrument

ABSTRACT

A reference voltage generation circuit includes a gamma correction resistor circuit which outputs reference voltages generated by resistively dividing voltages of two opposite ends of a resistor circuit to resistive division nodes, and high-potential-side-voltage and low-potential side-voltage supply circuits which supply a high-potential-side voltage and a low-potential-side voltage to the two opposite ends, respectively. The high-potential-side-voltage and low-potential side-voltage supply circuits supply the high-potential-side voltage and the low-potential-side voltage to the two opposite ends, respectively, by switching the high-potential-side voltage and the low-potential-side voltage for each of color components which faun one pixel, the high-potential-side voltage and the low-potential-side voltage being provided for each of the color components. The gamma correction resistor circuit supplies the reference voltages switched for each of the color components to reference voltage signal lines to be selected as inputs of driver sections which drive data lines of an electro-optical device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation patent application of U.S. Ser. No.11/065,773 filed Feb. 25, 2005, claiming priority to Japanese PatentApplication No. 2004-079051 filed Mar. 18, 2004, all of which areincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a reference voltage generation circuit,a data driver, a display device, and an electronic instrument.

A reduction in size and an increase in definition have been demanded fora display device represented by an electro-optical device such as aliquid crystal device. A liquid crystal device realizes a reduction inpower consumption and is generally provided in a portable electronicinstrument.

In recent years, an electroluminescent (hereinafter abbreviated as “EL”)device using an EL element has attracted attention. In particular, sincean organic EL device including an EL element formed by using a thin filmof an organic material is a self-emission type, a backlight becomesunnecessary, whereby a wide viewing angle is realized. Moreover, sincethe organic EL device has a high response speed in comparison with aliquid crystal panel, a color video display can be easily realized usinga simple configuration. In the case where such a display device isprovided as a display section of a portable telephone, an image displayrich in color tone due to an increase in the number of grayscales isrequired.

A drive signal for displaying an image is generally subjected to gammacorrection corresponding to display characteristics of a display device.The gamma correction is performed by using a gamma correction circuit.Taking a liquid crystal device as an example, a drive voltage correctedso as to realize an optimum pixel transmissivity can be output based ongrayscale data for performing a grayscale display by using the gammacorrection circuit. A data line is driven based on the drive voltage.

Grayscale characteristics (voltage-luminance characteristics) of aself-emission element such as an organic EL element differ in units ofcolor components which form one pixel. Therefore, gamma correction mustbe performed in units of color components. In the case of outputting avoltage obtained by dividing a predetermined range of voltage using aresistor element as the drive voltage, gamma correction may be realizedby selectively outputting the drive voltage corresponding to thegrayscale data selected from among a plurality of voltages divided andcorrected corresponding to the grayscale characteristics.

However, in the case where gamma correction circuits which realize sucha gamma correction are provided in units of data lines of a panelincluding organic EL elements arranged in the shape of a matrix, theoutput pitch of a data line driver circuit which drives the data linesis limited. Since the interconnect pitch of the data lines must bereduced in order to increase the definition of the display image, a dataline driver circuit which deals with an increase in definition cannot beprovided if the gamma correction circuits are provided as describedabove. Moreover, since current flows through the resistor element ofeach gamma correction circuit, power consumption cannot be reduced (seeFIGS. 1 and 6 of Japanese Patent Application Laid-open No. 2001-290457,for example).

BRIEF SUMMARY OF THE INVENTION

A first aspect of the present invention relates to a reference voltagegeneration circuit for generating a plurality of reference voltagesincluding a reference voltage selected corresponding to grayscale data,the reference voltage generation circuit including:

a gamma correction resistor circuit which includes a resistor circuitand outputs the reference voltages generated by resistively dividingvoltages of two opposite ends of the resistor circuit to a plurality ofresistive division nodes; and

first and second voltage supply circuits which supply ahigh-potential-side voltage and a low-potential-side voltage to the twoopposite ends of the resistor circuit, respectively,

wherein the first and second voltage supply circuits supply at least oneof the high-potential-side voltage and the low-potential-side voltage tothe two opposite ends of the resistor circuit, respectively, byswitching the high-potential-side voltage and the low-potential-sidevoltage for each of color components which form one pixel, thehigh-potential-side voltage and the low-potential-side voltage beingprovided for each of the color components, and

wherein the gamma correction resistor circuit supplies each of thereference voltages to one of a plurality of reference voltage signallines to be selected as inputs of first and second driver sections, thereference voltages being switched for each of the color components, andthe first and second driver sections respectively driving first andsecond data lines of an electro-optical device.

A second aspect of the present invention relates to a data driver fordriving a plurality of data lines of an electro-optical device includinga plurality of scan lines and the data lines based on grayscale data,the data driver including:

the above reference voltage generation circuit;

a data voltage generation circuit which outputs reference voltages amongthe plurality of reference voltages corresponding to first and secondgrayscale data as first and second data voltages;

a first driver section which drives the first data line based on thefirst data voltage; and

a second driver section which drives the second data line based on thesecond data voltage.

A third aspect of the present invention relates to a data driver fordriving a plurality of data lines of an electro-optical device includinga plurality of scan lines and the data lines based on grayscale data,the data driver including:

the above reference voltage generation circuit;

a multiplexer circuit which multiplexes the grayscale data for each ofthe color components of one pixel by time division;

a data voltage generation circuit which outputs reference voltages amongthe plurality of reference voltages corresponding to first and secondgrayscale data as first and second data voltages, the first and secondgrayscale data being multiplexed by the multiplexer circuit;

a first driver section which drives the first data line based on thefirst data voltage; and

a second driver section which drives the second data line based on thesecond data voltage.

A fourth aspect of the present invention relates to a display deviceincluding:

a plurality of scan lines;

a plurality of data lines;

a plurality of pixels specified by the scan lines and the data lines;

a scan driver which scans the scan lines; and

one of the above data drivers which drive the data lines of the displaydevice.

A fifth aspect of the present invention relates to display deviceincluding:

a plurality of scan lines;

a plurality of data lines;

a plurality of color component data lines provided for each of colorcomponents which form one pixel;

a plurality of pixels specified by the scan lines and the colorcomponent data lines;

a scan driver which scans the scan lines;

one of the above data drivers which drive the data lines of the displaydevice; and

a plurality of demultiplexers, each of the demultiplexers being providedfor one of the data lines and electrically connecting the one of thedata lines with corresponding one of the color component data lines insynchronization with a time division timing of the grayscale data.

A sixth aspect of the present invention relates to an electronicinstrument including one of the above display devices.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram showing a display device in an embodiment ofthe present invention.

FIG. 2 shows an electrical equivalent circuit of an example of thepixels shown in FIG. 1.

FIG. 3 shows an organic EL element.

FIG. 4 shows the scan line driver circuit shown in FIG. 1.

FIG. 5 is a block diagram showing the data line driver circuit shown inFIG. 1.

FIG. 6 is a circuit diagram showing the shift register, the data latch,and the line latch shown in FIG. 5.

FIG. 7 is a timing chart showing an operation example of the shiftregister and the data latch shown in FIG. 6.

FIG. 8 shows the multiplexer circuit, the DAC, and the output buffershown in FIG. 6.

FIG. 9 schematically shows the reference voltage select ROM circuitshown in FIG. 8.

FIG. 10 is a timing chart showing an operation example of the referencevoltage select ROM circuit.

FIG. 11 shows an example of voltage-luminance characteristics of theorganic EL elements for each color component.

FIG. 12 is a block diagram showing the reference voltage generationcircuit in an embodiment of the present invention.

FIG. 13 is a circuit diagram showing the gamma correction resistorcircuit shown in FIG. 12.

FIG. 14 shows an equivalent circuit of a pixel of an active matrix typedisplay panel.

FIG. 15 is a block diagram showing the high-potential-side voltagesupply circuit shown in FIG. 12.

FIG. 16 is a circuit diagram showing the voltage-follower-connectedoperational amplifier shown in FIG. 15.

FIG. 17 is a block diagram showing the low-potential-side voltage supplycircuit shown in FIG. 12.

FIG. 18 is a circuit diagram showing the voltage-follower-connectedoperational amplifier shown in FIG. 17.

FIG. 19 is a block diagram showing the gamma correction control circuitshown in FIG. 12.

FIG. 20 is a circuit diagram showing the hue control timing circuitshown in FIG. 19.

FIG. 21 is a timing chart showing an operation example of the referencevoltage generation circuit in an embodiment of the present invention anda data line driver circuit including the reference voltage generationcircuit.

FIG. 22 is a block diagram showing an example of an electronicinstrument to which the display device in an embodiment of the presentinvention is applied.

FIG. 23 is a perspective diagram showing a portable telephone as anexample of an electronic instrument to which the display device in anembodiment of the present invention is applied.

DETAILED DESCRIPTION OF THE EMBODIMENT

An embodiment of the present invention has been achieved in view of theabove-described technical problem, and may provide a reference voltagegeneration circuit, a data driver, a display device, and an electronicinstrument for performing gamma correction while reducing powerconsumption without limiting the output pitch to data lines of a displaypanel.

An embodiment of the present invention provides a reference voltagegeneration circuit for generating a plurality of reference voltagesincluding a reference voltage selected corresponding to grayscale data,the reference voltage generation circuit including:

a gamma correction resistor circuit which includes a resistor circuitand outputs the reference voltages generated by resistively dividingvoltages of two opposite ends of the resistor circuit to a plurality ofresistive division nodes; and

first and second voltage supply circuits which supply ahigh-potential-side voltage and a low-potential-side voltage to the twoopposite ends of the resistor circuit, respectively,

wherein the first and second voltage supply circuits supply at least oneof the high-potential-side voltage and the low-potential-side voltage tothe two opposite ends of the resistor circuit, respectively, byswitching the high-potential-side voltage and the low-potential sidevoltage for each of color components which form one pixel, thehigh-potential-side voltage and the low-potential-side voltage beingprovided for each of the color components, and

wherein the gamma correction resistor circuit supplies each of thereference voltages to one of a plurality of reference voltage signallines to be selected as inputs of first and second driver sections, thereference voltages being switched for each of the color components, andthe first and second driver sections respectively driving first andsecond data lines of an electro-optical device.

In this embodiment, the high-potential-side voltage and thelow-potential-side voltage supplied to either end of the resistorcircuit of the gamma correction resistor circuit are changed in units ofcolor components. Therefore, the reference voltages output from thegamma correction resistor circuit are changed in units of colorcomponents. This enables appropriate gamma correction to be performed inunits of color components even if the grayscale characteristics differin units of color components.

In this embodiment, since the gamma correction resistor circuit suppliesthe reference voltages to the reference voltage signal lines used incommon for the first and second driver sections which respectively drivethe first and second data lines of the electro-optical device, it isunnecessary to provide the reference voltage generation circuits in dataline units, whereby the data line output pitch of a data driverincluding the reference voltage generation circuit is prevented frombeing limited. This makes it possible to contribute to providing a datadriver which deals with an increase in definition.

In this embodiment, since one reference voltage generation circuit canbe used to drive a plurality of data lines, the amount of currentflowing through the resistor circuit for gamma correction can besignificantly reduced in comparison with the case of providing thereference voltage generation circuits in data line units.

With this reference voltage generation circuit,

the gamma correction resistor circuit may include a correction switchcircuit inserted between two of the resistance division nodes, and

the correction switch circuit may include a resistor element and aswitch element, and may electrically connect or disconnect the tworesistance division nodes into which the correction switch circuit isinserted, the resistor element and the switch element being connected inseries.

With this reference voltage generation circuit, the gamma correctionresistor circuit may cause at least one of the reference voltages todiffer for each of the color components.

According to this embodiment, since the resistance between the resistivedivision nodes between which the correction switch circuit is insertedcan be finely adjusted, the reference voltages can be finely adjusted inunits of color components corresponding to display characteristics andmanufacturing variation of the electro-optical device and visualcharacteristics of the human eye. Therefore, a reference voltagegeneration circuit which realizes excellent display characteristicswhile reducing power consumption can be provided.

With this reference voltage generation circuit,

the color components which form one pixel may include an R component, aG component, and a B component, and

a difference between the high-potential-side voltage and thelow-potential-side voltage for the R component may be greater than adifference between the high-potential-side voltage and thelow-potential-side voltage for the G component, and the differencebetween the high-potential-side voltage and the low-potential-sidevoltage for the G component may be greater than a difference between thehigh-potential-side voltage and the low-potential-side voltage for the Bcomponent.

According to this embodiment, a reference voltage generation circuit forrealizing gamma correction suitable for an electro-optical device havinggrayscale characteristics in which the B component has the highestemission start voltage and steeply rises in luminance corresponding tothe applied voltage and the R component has a wider voltage range up tothe point where a predetermined luminance is reached than the Gcomponent can be provided.

With this reference voltage generation circuit,

the color components which form one pixel may include an R component, aG component, and a B component, and

the high-potential-side voltage for the B component may be the lowestamong the high-potential-side voltage for the R component, thehigh-potential-side voltage for the G component, and thehigh-potential-side voltage for the B component.

According to this embodiment, a reference voltage generation circuit forrealizing gamma correction suitable for an electro-optical device havinggrayscale characteristics in which the B component has the highestemission start voltage and steeply rises in luminance corresponding tothe applied voltage can be provided.

With this reference voltage generation circuit,

the first voltage supply circuit may include avoltage-follower-connected operational amplifier, and

an output of the operational amplifier may be driven by a p-channeldriver transistor.

In this embodiment, it is necessary to increase the potential of one endof the resistor circuit toward the high potential side instead ofdecreasing the potential of the output of the first voltage supplycircuit. Therefore, the number of unnecessary current paths can bereduced in comparison with the case of using a class-AB operationalamplifier circuit having a configuration which decreases the potentialof the output of the first voltage supply circuit, whereby powerconsumption can be reduced.

With this reference voltage generation circuit,

the second voltage supply circuit may include avoltage-follower-connected operational amplifier, and

an output of the operational amplifier may be driven by a n-channeldriver transistor.

In this embodiment, it is necessary to decrease the potential of theother end of the resistor circuit toward the low potential side insteadof increasing the potential of the output of the second voltage supplycircuit. Therefore, the number of unnecessary current paths can bereduced in comparison with the case of using a class-AB operationalamplifier circuit having a configuration which increases the potentialof the output of the second voltage supply circuit, whereby powerconsumption can be reduced.

With this reference voltage generation circuit,

the grayscale data may be multiplexed by time division for each of thecolor components which form one pixel, and

the first and second voltage supply circuits may supply at least one ofthe high-potential-side voltage and the low-potential-side voltage tothe two opposite ends of the resistor circuit, respectively, byswitching the high-potential-side voltage and the low-potential-sidevoltage for each of the color components at a time division timing ofeach of the color components of the grayscale data.

According to this embodiment, since it is unnecessary to providecircuits for selecting the reference voltage corresponding to thegrayscale data from among the reference voltages in units of colorcomponents, the configuration of a data driver including the referencevoltage generation circuit can be simplified.

An embodiment of the present invention provides a data driver fordriving a plurality of data lines of an electro-optical device includinga plurality of scan lines and the data lines based on grayscale data,the data driver including:

the above reference voltage generation circuit;

a data voltage generation circuit which outputs reference voltages amongthe plurality of reference voltages corresponding to first and secondgrayscale data as first and second data voltages;

a first driver section which drives the first data line based on thefirst data voltage; and

a second driver section which drives the second data line based on thesecond data voltage.

An embodiment of the present invention provides a data driver fordriving a plurality of data lines of an electro-optical device includinga plurality of scan lines and the data lines based on grayscale data,the data driver including:

the above reference voltage generation circuit;

a multiplexer circuit which multiplexes the grayscale data for each ofthe color components of one pixel by time division;

a data voltage generation circuit which outputs reference voltages amongthe plurality of reference voltages corresponding to first and secondgrayscale data as first and second data voltages, the first and secondgrayscale data being multiplexed by the multiplexer circuit;

a first driver section which drives the first data line based on thefirst data voltage; and

a second driver section which drives the second data line based on thesecond data voltage.

According to this embodiment, a data driver which performs gammacorrection while reducing power consumption without limiting the outputpitch to the data lines of the electro-optical device can be provided.Moreover, a data driver which drives the data lines of theelectro-optical device by performing appropriate gamma correction inunits of color components, even if the grayscale characteristics differin units of color components, can be provided.

An embodiment of the present invention provides a display deviceincluding:

a plurality of scan lines;

a plurality of data lines;

a plurality of pixels specified by the scan lines and the data lines;

a scan driver which scans the scan lines; and

one of the above data drivers which drive the data lines of the displaydevice.

An embodiment of the present invention provides a display deviceincluding:

a plurality of scan lines;

a plurality of data lines;

a plurality of color component data lines provided for each of colorcomponents which form one pixel;

a plurality of pixels specified by the scan lines and the colorcomponent data lines;

a scan driver which scans the scan lines;

one of the above data drivers which drive the data lines of the displaydevice; and

a plurality of demultiplexers, each of the demultiplexers being providedfor one of the data lines and electrically connecting the one of thedata lines with corresponding one of the color component data lines insynchronization with a time division timing of the grayscale data.

With any of these display devices, each of the pixels may include anelectroluminescent element.

According to this embodiment, a display device which realizes anincrease in definition by reducing the interconnect pitch of the datalines and enables appropriate gamma correction in units of colorcomponents while reducing power consumption can be provided.

An embodiment of the present invention provides an electronic instrumentincluding one of the above display devices.

According to this embodiment, an electronic instrument including adisplay device which displays a high-definition image by performingappropriate gamma correction in units of color component while reducingpower consumption can be provided.

The embodiments of the present invention are described below in detailwith reference to the drawings. Note that the embodiments describedhereunder do not in any way limit the scope of the invention defined bythe claims laid out herein. Note also that not all of the elements ofthese embodiments should be taken as essential requirements to the meansof the present invention.

1. Display Device

FIG. 1 is a block diagram showing a display device in an embodiment ofthe present invention.

A display device 10 in this embodiment includes a display panel 20, ascan line driver circuit (scan driver) 30, a data line driver circuit(data driver) 40, and a display controller 50. The display device 10does not necessarily include all of these circuit blocks. The displaydevice 10 may have a configuration in which some of the circuit blocksare omitted.

The following description is given on the assumption that the displaypanel 20 is an organic EL panel. However, the present invention is notlimited thereto.

The display panel (electro-optical device in a broad sense) 20 includesa plurality of scan lines (gate lines in a narrow sense), a plurality ofdata lines (source lines in a narrow sense), and pixels specified by thescan lines and the data lines.

The display panel 20 is formed by using a low-temperature poly-silicon(hereinafter abbreviated as “LTPS”) process. According to the LTPSprocess, a switch circuit, a driver circuit, and the like can bedirectly formed on a panel substrate (glass substrate, for example) onwhich a pixel including a switch element (thin film transistor (TFT),for example) and the like is formed. Therefore, since the number ofparts can be reduced, the size and weight of the display panel can bereduced. Moreover, LTPS enables the pixel size to be reduced whilemaintaining the aperture ratio by applying a conventional siliconprocess technology. Furthermore, since LTPS has a high charge mobilityand a small parasitic capacitance in comparison with amorphous silicon(a-Si), a display drive which cannot be realized by a display panelformed by using a conventional silicon process can be achieved.

The display panel 20 includes demultiplexers formed on a panel substratein data lines units. The demultiplexer distributes drive signals outputfrom the data line driver circuit 40 by time division in units of colorcomponents to color component data lines provided in units of colorcomponents. This prevents the output pitch of the data line drivercircuit 40 from being reduced to a large extent. In this case, thedisplay panel 20 includes a plurality of scan lines, a plurality of datalines, a plurality of color component data lines, a plurality of pixels(display elements), and a plurality of demultiplexers. The colorcomponent data lines are provided in units of color components whichform one pixel. A pixel is specified by one of the scan lines and one ofthe color component data lines. The demultiplexers are provided in dataline units. The demultiplexer electrically connects the data line withone of the color component data lines in the number of color componentscorresponding to that data line in synchronization with a time divisiontiming of grayscale data.

The display panel 20 is formed on an active matrix substrate (glasssubstrate, for example). A plurality of scan lines G₁ to G_(M) (M is anatural number of two or more), arranged in a direction Y shown in FIG.1 and extending in a direction X, and a plurality of data lines S₁ toS_(N) (N is a natural number of two or more), arranged in the directionX and extending in the direction Y, are disposed on the active matrixsubstrate. The display panel 20 includes demultiplexers DMUX₁ toDMUX_(N), one of the data lines being connected with an input of each ofthe demultiplexers. An output of each of the demultiplexers is connectedwith an R component data line, a G component data line, and a Bcomponent data line provided in units of color components which form onepixel. Therefore, R component data lines RS₁ to RS_(N), G component datalines GS₁ to GS_(N), and B component data lines BS₁ to BS_(N), arrangedin the direction X and extending in the direction Y, are disposed on thedisplay panel 20.

Pixels (display elements) DER_(KL), DEG_(KL), and DEB_(KL) arerespectively provided at positions corresponding to the intersectingpoints of the scan line G_(K) (1≦K≦M, K is a natural number) and the Rcomponent data line RS_(L) (1≦L≦N, L is a natural number), the Gcomponent data line GS_(L), and the B component data line BS_(L).

FIG. 2 shows an electrical equivalent circuit of an example of thepixels DER_(KL), DEG_(KL), and DEBT shown in FIG. 1. Each pixel includesan organic EL element. Each pixel has the same configuration, and aluminescent material of the organic EL element differs in units of colorcomponents.

Taking the pixel DER_(KL) provided at the position corresponding to theintersecting point of the scan line G_(K) and the R component data lineRS_(L) as an example, the pixel DER_(KL) includes a switching transistorSTFT_(KLR), a driver transistor DTFT_(KLR), a storage capacitorCL_(KLR), and an organic EL element OLED_(KLR).

A gate of the switching transistor STFT_(KLR) is connected with the scanline G_(K). A source of the switching transistor STFT_(KLR) is connectedwith the R component data line RS_(L). A drain of the switchingtransistor STFT_(KLR) is connected with a gate of the driver transistorDTFT_(KLR). A given high-potential-side power supply voltage VDD issupplied to a source (drain) of the driver transistor DTFT_(KLR). Ananode (anode electrode) of the organic EL element OLED_(KLR) isconnected with a drain (source) of the driver transistor DTFT_(KLR). Aground power supply voltage VSS is supplied to a cathode (cathodeelectrode) of the organic EL element OLED_(KLR). The storage capacitorCL_(KLR) is inserted between the gate of the driver transistorDTFT_(KLR) and a power supply line to which the ground power supplyvoltage VSS is supplied.

When the switching transistor STFT_(KLR) is turned ON upon applicationof a scan voltage to the selected scan line G_(K), a data voltage of theR component data line RS_(L) is applied to one end of the storagecapacitor CL_(KLR). Therefore, an electric charge corresponding to thedata voltage of the R component data line RS_(L) is charged into thestorage capacitor CL_(KLR).

The data voltage of the R component data line RS_(L) is applied to thegate of the driver transistor DTFT_(KLR). This causes the drivertransistor DTFT_(KLR) to be turned ON, whereby voltage is supplied tothe organic EL element OLED_(KLR) in the forward direction. Since thevoltage at one end of the storage capacitor CL_(KLR) is applied to thegate of the driver transistor DTFT_(KLR) after the switching transistorSTFT_(KLR) has been turned OFF, the voltage is continuously supplied tothe organic EL element OLED_(KLR) in the forward direction.

FIG. 3 shows the organic EL element OLED_(KLR).

In the organic EL element OLED_(KLR), a transparent electrode (indiumtin oxide (ITO), for example), which functions as an anode 62 providedas the data line, is formed on a glass substrate 60. A cathode 64provided as the scan line is fanned above the anode 62. An organic layerincluding a luminescent layer and the like is formed between the anode62 and the cathode 64.

The organic layer includes a hole transport layer 66 formed on the uppersurface of the anode 62, a luminescent layer 68 formed on the uppersurface of the hole transport layer 66, and an electron transport layer70 formed between the luminescent layer 68 and the cathode 64.

A hole from the anode 62 and an electron from the cathode 64 arerecombined in the luminescent layer 68 by applying a potentialdifference between the data line and the scan line, specifically, byapplying a potential difference between the anode 62 and the cathode 64.The molecules of the luminescent layer 68 are excited by the energy thusgenerated, and the energy released when the molecules return to theground state becomes light. The light passes through the anode 62 formedof a transparent electrode and the glass substrate 60.

A color image can be displayed by changing the colors emitted from theluminescent layer 68 in units of color components.

In FIG. 1, the scan line driver circuit 30 scans (sequentially drives)the scan lines G₁ to G_(M) of the display panel 20.

The data line driver circuit 40 drives the data lines S₁ to S_(N) of thedisplay panel 20 based on grayscale data. The data line driver circuit40 drives the data lines using the drive signals multiplexed by timedivision in units of color components.

The display controller 50 controls the scan line driver circuit 30 andthe data line driver circuit 40 according to the content set by a hostsuch as a central processing unit (CPU) (not shown). In more detail, thedisplay controller 50 provides an operation mode setting and supplies ahorizontal synchronization signal and a vertical synchronization signalgenerated therein to the scan line driver circuit 30 and the data linedriver circuit 40, for example.

In the display device 10 having such a configuration, the scan linedriver circuit 30 and the data line driver circuit 40 drive the displaypanel 12 in combination based on grayscale data supplied from theoutside under control of the display controller 50.

In FIG. 1, the display device 10 includes the display controller 50.However, the display controller 50 may be provided outside the displaydevice 10. Or, the host may be included in the display device 10together with the display controller 50. Some or all of the scan linedriver circuit 30, the data line driver circuit 40, and the displaycontroller 50 may be formed on the display panel 20.

In FIG. 1, a display driver may be formed as a semiconductor device(integrated circuit or IC) by integrating the scan line driver circuit30 and the data line driver circuit 40. The display driver may includethe display controller 50.

1.1 Scan Line Driver Circuit

FIG. 4 shows the scan line driver circuit 30 shown in FIG. 1.

The scan line driver circuit 30 includes a shift register 32 and anoutput buffer 34.

The shift register 32 includes a plurality of flip-flops which areprovided corresponding to the scan lines and are sequentially connected.The shift register 32 holds an enable input-output signal EIO in theflip-flop in synchronization with a clock signal CLK, and sequentiallyshifts the enable input-output signal EIO to the adjacent flip-flops insynchronization with the clock signal CLK. The enable input-outputsignal EIO input to the shift register 32 is the verticalsynchronization signal supplied from the display controller 50.

The output buffer 34 drives the scan line by buffering the shift outputfrom the shift register 32 and outputting the shift output to the scanline.

1.2 Data Line Driver Circuit

FIG. 5 is a block diagram showing the data line driver circuit 40 shownin FIG. 1. The following description is given on the assumption that thegrayscale data for one pixel is 18 bits (grayscale data for each colorcomponent is six bits) for convenience of description. However, thepresent invention is not limited thereto.

The data line driver circuit (data driver) 40 includes a shift register41, a data latch 42, a line latch 43, a multiplexer circuit 44, adigital-to-analog converter (DAC) (data voltage generation circuit in abroad sense) 45, a reference voltage generation circuit 46, and anoutput buffer 47.

The shift register 41 includes a plurality of flip-flops which areprovided corresponding to the data lines and are sequentially connected.The shift register 41 holds the enable input-output signal EIO insynchronization with the clock signal CLK, and sequentially shifts theenable input-output signal EIO to the adjacent flip-flops insynchronization with the clock signal CLK.

Grayscale data (DIO) is input to the data latch 42 from the displaycontroller 50 in units of 18 bits (6 bits (grayscale data)×3 (each colorof RGB)), for example. The data latch 42 latches the grayscale data(DIO) in synchronization with the enable input-output signal EIOsequentially shifted by the flip-flops of the shift register 41.

The line latch 43 latches the grayscale data in one horizontal scan unitlatched by the data latch 42 in synchronization with a horizontalsynchronization signal LP supplied from the display controller 50.

The multiplexer circuit 44 generates multiplexed data in which thegrayscale data for the R component, the G component, and the B componentwhich form one pixel is multiplexed by time division. The time divisiontiming of the multiplexer circuit 44 is set so that the grayscale datafor the R component, the G component, and the B component istime-divided within one horizontal scan period.

The DAC 45 generates an analog data voltage (drive voltage in a broadsense) supplied to the data line. In more detail, the DAC 45 selects oneof a plurality of reference voltages from the reference voltagegeneration circuit 46 based on the digital multiplexed data from themultiplexer circuit 44, and outputs an analog data voltage correspondingto the digital grayscale data included in the multiplexed data.

The reference voltage generation circuit 46 generates a plurality ofreference voltages. The reference voltages are used in data line units.Specifically, the analog data voltage corresponding to the digitalgrayscale data included in the multiplexed data is selected from thereference voltages output from the reference voltage generation circuit46 in data line units.

The output buffer 47 drives the data line by buffering the data voltagefrom the DAC 45 and outputting the data voltage to the data line. Inmore detail, the output buffer 47 includes voltage-follower-connectedoperational amplifier circuits (driver sections in a broad sense)provided in data line units. Each of the operational amplifier circuitsconverts the data voltage from the DAC 47 by impedance conversion, andoutputs the converted data voltage to the data line.

FIG. 6 is a circuit diagram showing the shift register 41, the datalatch 42, and the line latch 43 shown in FIG. 5.

The shift register 41 includes first to N-th DFFs DFF2-1 to DFF2-N. Inthe following description, the i-th (1≦i≦N, i is an integer) DFF isindicated by DFF2-i. The shift register 41 is formed by connecting theDFFs DFF2-1 to DFF2-N in series. Specifically, a data output terminal Qof the DFF DFF2-j (1≦j≦N−1, j is an integer) is connected with a datainput terminal D of the DFF DFF2-(j+1) in the subsequent stage.

Shift outputs SFO1 to SFON are output from the data output terminals Qof the DFFs DFF2-1 to DFF2-N. The enable input-output signal EIO isinput to the data input terminal D of the DFF DFF2-1. The clock signal(dot clock signal) CLK is input to clock input terminals C of the DFFsDFF2-1 to DFF2-N.

The data latch 42 includes first to N-th latch DFFs. In the followingdescription, the i-th (1≦i≦N, i is an integer) latch DFF is indicated byLDFFi. The latch DFF LDFF holds a signal input to a data input terminalD at the falling edge of a signal input to a clock input terminal C. Thelatch DFF LDFF holds data in the number of bits of the grayscale datawhich forms one pixel. Specifically, 18-bit data, of which the number ofbits is the sum of the number of bits “6” of the R component grayscaledata, the number of bits “6” of the G component grayscale data, and thenumber of bits “6” of the B component grayscale data, is input to thedata input terminal D of each latch DFF LDFF. The shift output SFOi fromthe shift register 41 is supplied to the clock input terminal C of thelatch DFF LDFFi. Latch data LATi is data from the data output terminal Qof the latch DFF LDFFi. Grayscale latch data, which is the grayscaledata DIO synchronized with the falling edge of the clock signal CLK, isinput to the data input terminals D of the latch DFFs LDFF1 to LDFFN.

The line latch 43 includes first to N-th line latch DFFs. In thefollowing description, the i-th (1≦i≦N, i is an integer) line latch DFFis indicated by LLDFFi. The line latch DFF LLDFFi holds data in thenumber of bits of the grayscale data which forms one pixel. Thehorizontal synchronization signal LP is supplied to a clock inputterminal C of the line latch DFF LLDFFi. Line latch data LLATi is datafrom a data output terminal Q of the line latch DFF LLDFFi. The dataoutput terminal Q of the latch DFF LDFFi is connected with a data inputterminal D of the line latch DFF LLDFFi.

The DFFs DFF1-1 to DFF1-N, LDFF1 to LDFFN, and LLDFF1 to LLDFFN areinitialized by an inversion reset signal (not shown).

FIG. 7 is a timing chart showing an operation example of the shiftregister 41 and the data latch 42 shown in FIG. 6.

The grayscale data for one pixel including the R component grayscaledata, the G component grayscale data, and the B component grayscale datais sequentially supplied to the data latch 42 as the grayscale data DIOin synchronization with the clock signal CLK.

The enable input-output signal EIO is set at the H level correspondingto the head position of the grayscale data DIO. In the shift register41, the shift operation of the enable input-output signal EIO isperformed. Specifically, the shift register 41 stores the enableinput-output signal EIO at the rising edge of the clock signal CLK. Theshift register 41 sequentially outputs pulses shifted in synchronizationwith the rising edge of the clock signal CLK as the shift outputs SFO1to SFON in each stage.

The data latch 42 stores the grayscale latch data at the falling edge ofthe shift output from each stage of the shift register 41. As a result,the data latch 42 stores the grayscale latch data in the order of thelatch DFFs LDFF1, LDFF2, . . . . The grayscale data stored in the latchDFFs LDFF1 to LDFFN is respectively output as the latch data LAT1 toLATN.

The line latch 43 latches the data stored in the data latch 42 in unitsof one horizontal scan period. The grayscale data for one horizontalscan latched by the line latch 43 is supplied to the multiplexer circuit44.

FIG. 8 shows the multiplexer circuit 44, the DAC 45, and the outputbuffer 47 shown in FIG. 6. FIG. 8 shows only the data lines S_(L) andS_(L+1) to which the line latch data LLATL and LLAT(L+1) is respectivelysupplied. However, the same description also applies to other datalines.

The line latch data LLATL includes 6-bit R component grayscale dataR_(L)D, 6-bit G component grayscale data G_(L)D, and 6-bit B componentgrayscale data B_(L)D. The line latch data LLAT(L+1) includes 6-bit Rcomponent grayscale data R_(L+1)D, 6-bit G component grayscale dataG_(L+1)D, and 6-bit B component grayscale data B_(L+1)D.

The multiplexer circuit 44 generates multiplexed data in data line unitsbased on an R component select signal Rsel, a G component select signalGsel, and a B component select signal Bsel. In more detail, themultiplexer circuit 44 includes multiplex switches MULSW₁ to MULSW_(N)in data line units. In FIG. 8, the multiplex switch MULSW_(L) providedcorresponding to the data line S_(L) generates 6-bit multiplexed dataMULD_(L) in which the R component grayscale data R_(L)D, the G componentgrayscale data G_(L)D, and the B component grayscale data B_(L)D aremultiplexed based on the R component select signal Rsel, the G componentselect signal Gsel, and the B component select signal Bsel. Themultiplex switch MULSW_(L+1) provided corresponding to the data lineS_(L+1) generates 6-bit multiplexed data MULD_(L+1) in which the Rcomponent grayscale data R_(L+1)D, the G component grayscale dataG_(L+1) D, and the B component grayscale data B_(L+1)D are multiplexedbased on the R component select signal Rsel, the G component selectsignal Gsel, and the B component select signal Bsel.

The DAC 45 includes reference voltage select read only memory (ROM)circuits VSEL₁ to VSEL_(N) provided in data line units. In FIG. 8, thereference voltage select ROM circuit VSEL_(L) provided corresponding tothe data line S_(L) selects one of the reference voltages from thereference voltage generation circuit 46 in units of color componentsbased on the multiplexed data MULD_(L). Specifically, the referencevoltage select ROM circuit VSEL_(L) selects one of the referencevoltages based on the R component grayscale data R_(L)D multiplexed intothe multiplexed data MULD_(L). The reference voltage select ROM circuitVSEL_(L) selects one of the reference voltages based on the G componentgrayscale data G_(L)D multiplexed into the multiplexed data MULD_(L).The reference voltage select ROM circuit VSEL_(L) selects one of thereference voltages based on the B component grayscale data B_(L)Dmultiplexed into the multiplexed data MULD_(L).

Since the number of bits of each color component grayscale data is six,the reference voltage generation circuit 46 generates 64 (=2⁶) types ofreference voltages V0 to V63. The reference voltage generation circuit46 outputs R component reference voltages V0R to V63R, G componentreference voltages V0G to V63G, or B component reference voltages V0B toV63B as the reference voltages V0 to V63 corresponding to the timedivision timing of the color component grayscale data of the multiplexeddata MULD₁ to MULD_(N).

The output buffer 47 includes a plurality of operational amplifiercircuits OPC₁ to OPC_(L) provided in data line units. In FIG. 8, theoperational amplifier circuit OPC_(L) drives the data line S_(L) basedon a data voltage DP_(L) output from the reference voltage select ROMcircuit VSEL_(L).

FIG. 9 schematically shows the reference voltage select ROM circuitVSEL_(L) shown in FIG. 8. FIG. 9 shows a configuration of the referencevoltage select ROM circuit VSEL_(L). However, the reference voltageselect ROM circuits VSEL₁ to VSEL_(N) have the same configuration as thereference voltage select ROM circuit VSEL_(L).

Non-inverted data D5 to D0 which is the 6-bit multiplexed data MULD_(L)and inverted data XD5 to XD0 obtained by reversing each bit of thenon-inverted data D5 to D0 are input to the reference voltage select ROMcircuit VSEL_(L). One of 64 reference voltage signal lines to which thereference voltages V0 to V63 are supplied is electrically connected witha signal line to which the data voltage DP_(L) is supplied correspondingto the pattern of each bit of the non-inverted data D5 to D0 and theinverted data XD5 to XD0.

For example, the non-inverted data D5 is supplied to a gate of atransistor element Q1, and a grayscale voltage signal line to which thereference voltage V63 is supplied is connected with a source of thetransistor element Q1. A source of a transistor Q2 is connected with adrain of the transistor Q1. The inverted data XD5 is supplied to a gateof the transistor Q2, and a source of a transistor Q3 (not shown) isconnected with a drain of the transistor Q2. However, a channel regionis formed in the transistor Q2 by ion implantation so that thetransistor Q2 is always in the ON state. One of the reference voltagescan be output as the data voltage DP_(L) based on the non-inverted dataD5 to D0 and the inverted data XD5 to XD0 by configuring the referencevoltage select ROM circuit VSEL_(L) as described above.

FIG. 10 is a timing chart showing an operation example of the referencevoltage select ROM circuit VSEL_(L). FIG. 10 shows an operation exampleof the reference voltage select ROM circuit VSEL_(L). However, theoperations of other reference voltage select ROM circuits are the sameas described below.

In an R component select period specified by the R component selectsignal Rsel, the R component reference voltages V0R to V63R are suppliedto the reference voltage select ROM circuit VSEL_(L) as the referencevoltages V0 to V63. In a G component select period specified by the Gcomponent select signal Gsel, the G component reference voltages V0G toV63G are supplied to the reference voltage select ROM circuit VSEL_(L)as the reference voltages V0 to V63. In a B component select periodspecified by the B component select signal Bsel, the B componentreference voltages V0B to V63B are supplied to the reference voltageselect ROM circuit VSEL_(L) as the reference voltages V0 to V63.

In the R component select period, one reference voltage corresponding tothe R component grayscale data R_(L)D is selected from among the Rcomponent reference voltages V0R to V63R, and the data line S_(L) isdriven based on the selected reference voltage. In the G componentselect period, one reference voltage corresponding to the G componentgrayscale data G_(L)D is selected from among the G component referencevoltages V0G to V63G, and the data line S_(L) is driven based on theselected reference voltage. In the B component select period, onereference voltage corresponding to the B component grayscale data B_(L)Dis selected from among the B component reference voltages V0B to V63B,and the data line S_(L) is driven based on the selected referencevoltage.

As described above, 64 types of reference voltages V0 to V63 for eachcolor component are selectively supplied to the reference voltage selectROM circuit VSEL_(L) in synchronization with the time division timing ofthe color component grayscale data in the multiplexed data MULD_(L). Thereference voltage select ROM circuit VSEL_(L) outputs the data voltageDP_(L) which is changed in potential in synchronization with the timedivision timing of the color component grayscale data in the multiplexeddata MULD_(L).

2. Reference Voltage Generation Circuit

FIG. 11 shows an example of voltage-luminance characteristics of theorganic EL elements for each color component. In FIG. 11, the horizontalaxis indicates the voltage applied to the organic EL element, and thevertical axis indicates the luminance of the organic EL element. FIG. 11shows the relationship between the applied voltage and the luminance ofthe organic EL element for each color component.

As shown in FIG. 11, the luminance differs in units of color componentseven if the applied voltage is the same. Therefore, in the case ofdriving a panel in which a pixel includes an organic EL element havingthe voltage-luminance characteristics shown in FIG. 11, it is necessaryto generate different data voltages in units of color components even ifthe grayscale data is the same for different color components.Therefore, the reference voltage generation circuit must change thereference voltages in units of color components.

As is clear from FIG. 11, the voltage at which the B component startsemitting light is higher in comparison with the R component and the Gcomponent. The B component has a higher luminance in comparison with theR component and the G component after emission of light has started. Thereference voltage generation circuit in this embodiment can generatedifferent reference voltages in units of color components taking suchvoltage-luminance characteristics (grayscale characteristics) intoconsideration.

The reference voltage generation circuit in this embodiment is describedbelow in detail.

FIG. 12 is a block diagram showing the reference voltage generationcircuit in an embodiment of the present invention.

A reference voltage generation circuit 100 shown in FIG. 12 may be usedas the reference voltage generation circuit 46 shown in FIG. 5. Thereference voltage generation circuit 100 includes a gamma correctionresistor circuit 110, a high-potential-side voltage supply circuit(first voltage supply circuit) 120, and a low-potential-side voltagesupply circuit (second voltage supply circuit) 130.

FIG. 13 is a circuit diagram showing the gamma correction resistorcircuit 110 shown in FIG. 12.

The gamma correction resistor circuit 110 includes a resistor circuit112. A high-potential-side voltage VH and a low-potential-side voltageVL are supplied to either end of the resistor circuit 112. The resistorcircuit 112 generates a plurality of reference voltages, each of whichis generated by resistively dividing the voltage across the resistorcircuit 112. One of the reference voltage signal lines is connected witheach of a plurality of resistive division nodes of the resistor circuit112, and one of the reference voltages is output to each of thereference voltage signal lines.

In FIG. 12, the high-potential-side voltage supply circuit 120 suppliesthe high-potential-side voltage VH of the resistor circuit 112. Thehigh-potential-side voltage supply circuit 120 changes thehigh-potential-side voltage VH in units of color components which formone pixel, and supplies the high-potential-side voltage VH to one end ofthe resistor circuit 112.

The low-potential-side voltage supply circuit 130 supplies thelow-potential-side voltage VL of the resistor circuit 112. Thelow-potential-side voltage supply circuit 130 changes thelow-potential-side voltage VL in units of color components which formone pixel, and supplies the low-potential-side voltage VL to one end ofthe resistor circuit 112.

In this embodiment, it suffices that the high-potential-side voltagesupply circuit 120 and the low-potential-side voltage supply circuit 130be able to change at least one of the high-potential-side voltage andthe low-potential-side voltage in units of color components which formone pixel.

The gamma correction resistor circuit 110 thus generates 64 types ofreference voltages V0 to V63, and supplies the reference voltages V0 toV63 to each of the reference voltage select ROM circuits having theconfiguration shown in FIG. 9 and provided in data line units.Specifically, the gamma correction resistor circuit 110 outputs aplurality of reference voltages changed in units of color components toa plurality of reference voltage signal lines for selecting the voltagesfor the operational amplifier circuits OPC_(L) and OPC_(L+1) (first andsecond driver sections) to respectively drive the data lines S_(L) andS_(L+1) (first and second data lines) of the display panel(electro-optical device) 20.

In this embodiment, the grayscale data is multiplexed by time divisionin units of color components which form one pixel, and thehigh-potential-side voltage supply circuit 120 and thelow-potential-side voltage supply circuit 130 change at least one of thehigh-potential-side voltage and the low-potential-side voltage in unitsof color components at a time division timing of each color component ofthe grayscale data, and supply the high-potential-side voltage and thelow-potential-side voltage to either end of the resistor circuit 112.

In FIG. 13, the gamma correction resistor circuit 110 may furtherinclude at least one correction switch circuit in addition to theresistor circuit 112. The correction switch circuit is inserted betweentwo of the resistive division nodes of the resistor circuit 112. Thecorrection switch circuit includes a resistor element and a switchelement connected in series. The correction switch circuit electricallyconnects or disconnects the resistive division nodes between which thecorrection switch circuit is inserted. At least one of the referencevoltages can be caused to differ in units of color components by usingthe correction switch circuit.

In FIG. 13, the gamma correction resistor circuit 110 includes aplurality of correction switch circuits. In more detail, the gammacorrection resistor circuit 110 includes a plurality of correctionswitch circuits provided in the shape of a matrix.

In more detail, the gamma correction resistor circuit 110 includes aplurality of correction switch circuits ASW1-1 to ASW1-4, . . . ,ASW62-1 to ASW62-4, and ASW63-1 to ASW63-4 connected between theresistive division nodes of the resistor circuit 112. For example, thecorrection switch circuits ASW1-1 to ASW1-4 are inserted between tworesistive division nodes connected with two reference voltage signallines which supply the reference voltages V0 and V1. The correctionswitch circuits ASW62-1 to ASW62-4 are inserted between two resistivedivision nodes connected with two reference voltage signal lines whichsupply the reference voltages V61 and V62. The correction switchcircuits ASW63-1 to ASW63-4 are inserted between two resistive divisionnodes connected with two reference voltage signal lines which supply thereference voltages V62 and V63. The switch elements of the correctionswitch circuit ASW1-1 to ASW1-4 are ON/OFF controlled by correctionswitch control signals c1-1 to c1-4, respectively. The switch elementsof the correction switch circuit ASW62-1 to ASW62-4 are ON/OFFcontrolled by correction switch control signals c62-1 to c62-4,respectively. The switch elements of the correction switch circuitASW63-1 to ASW63-4 are ON/OFF controlled by correction switch controlsignals c63-1 to c63-4, respectively.

In this embodiment, the resistive dividing ratio between the resistivedivision nodes of the resistor circuit 112 can be caused to differ inunits of color components by using the correction switch controlsignals.

The resistances of the resistor elements of the correction switchcircuits connected between the same resistive division nodes may be thesame, or may differ at a predetermined ratio (1:2:4:8, for example). Inthis embodiment, it is preferable that the resistance between theresistive division nodes of the resistor circuit 112 have the followingrelationship.

FIG. 14 shows an equivalent circuit of a pixel of an active matrix typedisplay panel. FIG. 14 shows only the pixel DER_(KL), shown in FIG. 2.

It is known that the luminance of the organic EL element OLED_(KLR) isincreased in proportion to power consumption. When current which flowsthrough the organic EL element OLED_(KLR) is indicated by I, powerconsumption is proportional to I². Therefore, the luminance of theorganic EL element OLED_(KLR) is proportional to the second power of adrain current Id of the driver transistor DTFT_(KLR) shown in FIG. 14.

When a gate voltage and a threshold voltage of the driver transistorDTFT_(KLR) are respectively indicated by Vg and Vth, the drain currentId of the transistor in the saturation region is proportional to(Vg−Vth)². Specifically, the gate voltage Vg of the driver transistorDTFT_(KLR) and the luminance of the organic EL element OLED_(KLR) havealmost a linear relationship. Since the gate voltage Vg of the drivertransistor DTFT_(KLR) is almost equal to the data voltage of the Rcomponent data line RS_(L), it suffices that the reference voltages V0to V63 from which the data voltage is selected have almost a linearrelationship. This is realized by equalizing the resistance between theresistive division nodes of the resistor circuit 112. It is preferableto finely adjust the reference voltage by using the correction switchcircuit shown in FIG. 13 corresponding to the characteristics of thedisplay panel, manufacturing variation of the display panel, and visualcharacteristics of the human eye.

As described above, in the case of applying the reference voltagegeneration circuit 100 in this embodiment to a data line driver circuitwhich drives a panel including the pixel shown in FIG. 14, it ispreferable that the resistance between the resistive division nodes ofthe resistor circuit 112 be the same.

The reference voltage generation circuit 100 in this embodiment is notlimited to the resistance between the resistive division nodes of theresistor circuit 112. The reference voltage generation circuit 100 mayalso be applied to a data line driver circuit which drives a simplematrix type display panel including an organic EL element.

In FIG. 12, a selector 140 generates the correction switch controlsignals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4. Theselector 140 can output the correction switch control signals c1-1 toc1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4 in units of colorcomponents.

In more detail, R component correction switch control signals c1-1R toc1-4R, . . . , c62-1R to c62-4R, and c63-1R to c63-4R, G componentcorrection switch control signals c1-1G to c1-4G, . . . , c62-1G toc62-4G, and c63-1G to c63-4G, and B component correction switch controlsignals c1-1B to c1-4B, . . . , c62-1B to c62-4B, and c63-1B to c63-4Bare supplied to the selector 140. The selector 140 outputs the Rcomponent correction switch control signals c1-1R to c1-4R, . . . ,c62-1R to c62-4R, and c63-1R to c63-4R as the correction switch controlsignals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4 whenthe R component select signal Rsel is active. The selector 140 outputsthe G component correction switch control signals c1-1G to c1-4G, . . ., c62-1G to c62-4G, and c63-1G to c63-4G as the correction switchcontrol signals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4when the G component select signal Gsel is active. The selector 140outputs the B component correction switch control signals c1-1B toc1-4B, . . . , c62-1B to c62-4B, and c63-1B to c63-4B as the correctionswitch control signals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1to c63-4 when the B component select signal Bsel is active.

The R component correction switch control signals c1-1R to c1-4R, . . ., c62-1R to c62-4R, and c63-1R to c63-4R are generated based on a valueset in an R component gamma correction setting register 150-R. The Gcomponent correction switch control signals c1-1G to c1-4G, . . . ,c62-1G to c62-4G, and c63-1G to c63-4G are generated based on a valueset in a G component gamma correction setting register 150-G The Bcomponent correction switch control signals c1-1B to c1-4B, . . . ,c62-1B to c62-4B, and c63-1B to c63-4B are generated based on a valueset in a B component gamma correction setting register 150-B. The valuesare set in the R component gamma correction setting register 150-R, theG component gamma correction setting register 150-G, and the B componentgamma correction setting register 150-B by the display controller 50.

The reference voltage generation circuit 100 includes a gamma correctioncontrol circuit 160. The gamma correction control circuit 160 generatesthe R component select signal Rsel, the G component select signal Gsel,and the B component select signal Bsel. The R component select signalRsel, the G component select signal Gsel, and the B component selectsignal Bsel are generated so that these signals do not become active atthe same time. The gamma correction control circuit 160 may be providedoutside the reference voltage generation circuit 100.

The high-potential-side voltage supply circuit 120, thelow-potential-side voltage supply circuit 130, and the gamma correctioncontrol circuit 160 are described below.

FIG. 15 is a block diagram showing the high-potential-side voltagesupply circuit 120 shown in FIG. 12.

The high-potential-side voltage supply circuit 120 outputs one of an Rcomponent high-potential-side voltage VHR, a G componenthigh-potential-side voltage VHG, and a B component high-potential-sidevoltage VHB as the high-potential-side voltage VH. Therefore, thehigh-potential-side voltage supply circuit 120 includes ahigh-potential-side voltage supply switch HSW.

The high-potential-side voltage supply switch HSW outputs the Rcomponent high-potential-side voltage VHR as the high-potential-sidevoltage VH when the R component select signal Rsel is active. Thehigh-potential-side voltage supply switch HSW outputs the G componenthigh-potential-side voltage VHG as the high-potential-side voltage VHwhen the G component select signal Gsel is active. Thehigh-potential-side voltage supply switch HSW outputs the B componenthigh-potential-side voltage VHB as the high-potential-side voltage VHwhen the B component select signal Bsel is active.

The R component high-potential-side voltage VHR is output as one of aplurality of reference high-potential-side voltages obtained byresistively dividing a given voltage based on a value set in an Rcomponent high potential setting register 122-R. The G componenthigh-potential-side voltage VHG is output as one of a plurality ofreference high-potential-side voltages obtained by resistively dividinga given voltage based on a value set in a G component high potentialsetting register 122-G The B component high-potential-side voltage VHBis output as one of a plurality of reference high-potential-sidevoltages obtained by resistively dividing a given voltage based on avalue set in a B component high potential setting register 122-B.

The values are set in the R component high potential setting register122-R, the G component high potential setting register 122-G, and the Bcomponent high potential setting register 122-B by the displaycontroller 50.

As described above, in the high-potential-side voltage supply circuit120, one of the high-potential-side voltages generated in units of colorcomponents is selected by the high-potential-side voltage supply switchHSW. A voltage-follower-connected operational amplifier OPH converts theselected voltage by impedance conversion and outputs the convertedvoltage as the high-potential-side voltage VH.

FIG. 16 is a circuit diagram showing the voltage-follower-connectedoperational amplifier OPH shown in FIG. 15.

The output of the operational amplifier OPH is driven by a p-channeldriver transistor PT13. The operational amplifier OPH includes a firstdifferential section DIF1 and a first driver section DRV1, and may beformed by voltage-follower-connecting the first differential sectionDIF1 and the first driver section DRV1.

The first driver section DRV1 includes the p-channel driver transistorPT13, but does not include an n-channel driver transistor. The firstdriver section DRV1 includes the p-channel driver transistor PT13 and acurrent source IS12. The p-channel driver transistor PT13 is connectedwith the power supply voltage VOUT at one end, and is connected with theoutput of the operational amplifier OPH at the other end. The currentsource IS12 is connected with the ground power supply voltage VSS at oneend, and is connected with the output of the operational amplifier OPHat the other end. In FIG. 16, a capacitor CC1 is used for phasecompensation.

The first differential section DIF1 includes p-channel transistors PT11and PT12 of which gates are connected with an output DQ1 of the firstdifferential section DIF1, n-channel transistors NT11 and NT12 of whichgates are respectively connected with inputs I1 and XI1 of the firstdifferential section DIF1, and a current source IS11 provided on theside of the ground power supply voltage VSS.

The operational amplifier OPH is voltage-follower-connected in which anoutput Q1 is connected with the input XI1 (inverting input) of the firstdifferential section DIF1.

In the operational amplifier OPH having such a configuration, currentflows through only paths I11 and I12. Therefore, the operationalamplifier OPH can reduce the amount of unnecessary current in comparisonwith a class-AB operational amplifier circuit having three or morecurrent paths, whereby power consumption can be reduced.

In the operational amplifier OPH, the amount of current I12 flowingthrough the current source IS12 can be significantly reduced when it isunnecessary to decrease the voltage level of the output Q1 toward thelow potential side to a large extent. In the high-potential-side voltagesupply circuit 120 shown in FIG. 12, the operational amplifier OPH neednot decrease the voltage level of one end of the resistor circuit 112toward the low potential side, but must increase the voltage level ofone end of the resistor circuit 112 toward the high potential side.Therefore, power consumption can be reduced by configuring theoperational amplifier OPH as shown in FIG. 16.

FIG. 17 is a block diagram showing the low-potential-side voltage supplycircuit 130 shown in FIG. 12.

The low-potential-side voltage supply circuit 130 outputs one of an Rcomponent low-potential-side voltage VLR, a G componentlow-potential-side voltage VLG, and a B component low-potential-sidevoltage VLB as the low-potential-side voltage VL. Therefore, thelow-potential-side voltage supply circuit 130 includes alow-potential-side voltage supply switch LSW.

The low-potential-side voltage supply switch LSW outputs the R componentlow-potential-side voltage VLR as the low-potential-side voltage VL whenthe R component select signal Rsel is active. The low-potential-sidevoltage supply switch LSW outputs the G component low-potential-sidevoltage VLG as the low-potential-side voltage VL when the G componentselect signal Gsel is active. The low-potential-side voltage supplyswitch LSW outputs the B component low-potential-side voltage VLB as thelow-potential-side voltage VL when the B component select signal Bsel isactive.

The R component low-potential-side voltage VLR is output as one of aplurality of reference low-potential-side voltages obtained byresistively dividing a given voltage based on a value set in an Rcomponent low potential setting register 132-R. The G componentlow-potential-side voltage VLG is output as one of a plurality ofreference low-potential-side voltages obtained by resistively dividing agiven voltage based on a value set in a G component low potentialsetting register 132-G The B component low-potential-side voltage VLB isoutput as one of a plurality of reference low-potential-side voltagesobtained by resistively dividing a given voltage based on a value set ina B component low potential setting register 132-B.

The values are set in the R component low potential setting register132-R, the G component low potential setting register 132-G, and the Bcomponent low potential setting register 132-B by the display controller50.

As described above, in the low-potential-side voltage supply circuit130, one of the low-potential-side voltages generated in units of colorcomponents is selected by the low-potential-side voltage supply switchLSW. A voltage-follower-connected operational amplifier OPL converts theselected voltage by impedance conversion and outputs the convertedvoltage as the low-potential-side voltage VL.

FIG. 18 is a circuit diagram showing the voltage-follower-connectedoperational amplifier OPL shown in FIG. 17.

The output of the operational amplifier OPL is driven by an n-channeldriver transistor NT23. The operational amplifier OPL includes a seconddifferential section DIF2 and a second driver section DRV2, and may beformed by voltage-follower-connecting the second differential sectionDIF2 and the second driver section DRV2.

The second driver section DRV2 includes the n-channel driver transistorNT23, but does not include a p-channel driver transistor. The seconddriver section DRV2 includes the n-channel driver transistor NT23 and acurrent source IS22. The n-channel driver transistor NT23 is connectedwith the ground power supply voltage VSS at one end, and is connectedwith the output of the operational amplifier OPL at the other end. Thecurrent source IS22 is connected with the power supply voltage VOUT atone end, and is connected with the output of the operational amplifierOPL at the other end. In FIG. 18, a capacitor CC2 is used for phasecompensation.

The second differential section DIF2 includes n-channel transistors NT21and NT22 of which gates are connected with an output DQ2 of the seconddifferential section DIF2, p-channel transistors PT21 and PT22 of whichgates are respectively connected with inputs I2 and XI2 of the seconddifferential section DIF2, and a current source IS21 provided on theside of the power supply voltage VOUT.

The operational amplifier OPL is voltage-follower-connected in which anoutput Q2 is connected with the input XI2 (inverting input) of thesecond differential section DIF2.

In the operational amplifier OPL having such a configuration, currentflows through only paths I21 and I22. Therefore, the operationalamplifier OPL can reduce the amount of unnecessary current in comparisonwith a class-AB operational amplifier circuit having three or morecurrent paths, whereby power consumption can be reduced.

In the operational amplifier OPL, the amount of current I22 flowingthrough the current source IS22 can be significantly reduced when it isunnecessary to increase the voltage level of the output Q2 toward thehigh potential side to a large extent. In the low-potential-side voltagesupply circuit 130 shown in FIG. 12, the operational amplifier OPL neednot increase the voltage level of the other end of the resistor circuit112 toward the high potential side. Therefore, power consumption can bereduced by configuring the operational amplifier OPL as shown in FIG.18.

In this embodiment, in the case where the high-potential-side voltagesupply circuit 120 and the low-potential-side voltage supply circuit 130respectively supply the high-potential-side voltage VH and thelow-potential-side voltage VL according to the voltage-luminancecharacteristics shown in FIG. 11, it is preferable that thehigh-potential-side voltage VH and the low-potential-side voltage VL beas described below.

It is preferable that a difference ΔVR between the R componenthigh-potential-side voltage VHR and the R component low-potential-sidevoltage VLR be greater than a difference ΔVG between the G componenthigh-potential-side voltage VHG and the G component low-potential-sidevoltage VLG, and the difference ΔVG be greater than a difference ΔVBbetween the B component high-potential-side voltage VHB and the Bcomponent low-potential-side voltage VLB (ΔVR>ΔVG>ΔVB). As shown in FIG.11, since the B component has the highest emission start voltage andsteeply rises in luminance, the B component has the narrowest voltagerange when dividing a predetermined range of luminance by the number ofgrayscales. Moreover, since the R component has a wider voltage range upto the point where a predetermined luminance is reached after the startof light emission than the G component, the difference ΔVR is set to begreater than the difference ΔVG.

In regard to the resistance between the resistive division nodes of thegamma correction resistor circuit 110 for each color component, theresistance between the resistive division nodes for the B component isthe smallest for the same reason as described above.

It is preferable that the B component high-potential-side voltage VHB bethe lowest among the R component high-potential-side voltage VHR, the Gcomponent high-potential-side voltage VHG, and the B componenthigh-potential-side voltage VHB (VHR and VHG>VHB). This is because it ispreferable to divide the luminance by a plurality of grayscale levels ina wider voltage range, since the B component has the highest emissionstart voltage as shown in FIG. 11.

FIG. 19 is a block diagram showing the gamma correction control circuit160 shown in FIG. 12.

The gamma correction control circuit 160 includes a hue control timingcircuit 162. The hue control timing circuit 162 generates the Rcomponent select signal Rsel, the G component select signal Gsel, andthe B component select signal Bsel which specify the time divisiontiming of each color component. The hue control timing circuit 162 cangenerate the R component select signal Rsel, the G component selectsignal Gsel, and the B component select signal Bsel based on thehorizontal synchronization signal LP and the clock signal (dot clocksignal) CLK.

In more detail, the hue control timing circuit 162 generates the Rcomponent select signal Rsel based on a value set in an R componentdisplay time register 164-R. The hue control timing circuit 162generates the G component select signal Gsel based on a value set in a Gcomponent display time register 164-G The hue control timing circuit 162generates the B component select signal Bsel based on a value set in a Bcomponent display time register 164-B.

FIG. 20 is a circuit diagram showing the hue control timing circuit 162shown in FIG. 19.

R component display start time data and R component display end timedata set in the R component display time register 164-R are input to thehue control timing circuit 162. G component display start time data andG component display end time data set in the G component display timeregister 164-G and B component display start time data and B componentdisplay end time data set in the B component display time register 164-Bare input to the hue control timing circuit 162.

In the hue control timing circuit 162, a horizontal time counter HCOUNTincrements a count value CT in synchronization with the rising edge ofthe clock signal CLK, and supplies the count value CT to comparatorsCMP1-R, CMP2-R, CMP1-G, CMP2-G, CMP1-B, and CMP2-B.

The comparator CMP1-R compares the count value CT with the R componentdisplay start time data, and sets its output at the H level when thesevalues coincide. The comparator CMP2-R compares the count value CT withthe R component display end time data, and sets its output at the Hlevel when these values coincide. The remaining comparators are the sameas described above.

A reset-set flip-flop RSF-R sets its output (sets its output at the Hlevel) when the output from the comparator CMP1-R is set at the H level,and resets its output (sets its output at the L level) when the outputfrom the comparator CMP2-R is set at the H level. The output from thereset-set flip-flop RSF-R is the R component select signal Rsel. Thereset-set flip-flop RSF-R is also reset when the horizontalsynchronization signal LP is set at the H level.

Reset-set flip-flops RSF-G and RSF-B respectively output the G componentselect signal Gsel and the B component select signal Bsel in the samemanner as the reset-set flip-flop RSF-R.

FIG. 21 is a timing chart showing an operation example of the referencevoltage generation circuit in this embodiment and a data line drivercircuit including the reference voltage generation circuit.

The horizontal synchronization signal LP and the clock signal CLK areinput to the hue control timing circuit 162 of the gamma correctioncontrol circuit 160. When the count value incremented based on the clocksignal CLK coincides with the R component display start time data (E1),the R component select signal Rsel is set at the H level. When the countvalue coincides with the R component display end time data (E2), the Rcomponent select signal Rsel is set at the L level.

A period in which the R component select signal Rsel is set at the Hlevel is the R component select period. In the R component selectperiod, the high-potential-side voltage supply circuit 120 supplies theR component high-potential-side voltage VHR to one end of the resistorcircuit 112 as the high-potential-side voltage VH, and thelow-potential-side voltage supply circuit 130 supplies the R componentlow-potential-side voltage VLR to the other end of the resistor circuit112 as the low-potential-side voltage VL.

In the R component select period, the selector 140 outputs the Rcomponent correction switch control signals c1-1R to c1-4R, . . . ,c62-1R to c62-4R, and c63-1R to c63-4R as the correction switch controlsignals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4.Therefore, in the resistor circuit 112 of the gamma correction resistorcircuit 110, the resistance between the resistive division nodes iscorrected for the R component. Therefore, the reference voltages V0R toV63R gamma-corrected for the R component are output to the referencevoltage select ROM circuits as the reference voltages V0 to V63 throughthe reference voltage signal lines.

For example, the reference voltage select ROM circuit VSEL_(L) among thereference voltage select ROM circuits VSEL_(i) to VSEL_(N) selects oneof the reference voltages V0 to V63 as the data voltage DP_(L)R based onthe R component grayscale data R_(L)D. The operational amplifier circuitOPC_(L) drives the data line S_(L) of the display panel 20 based on thedata voltage DP_(L)R. The same description also applies to the referencevoltage select ROM circuits and the operational amplifier circuitsprovided corresponding to other data lines.

The R component select signal Rsel, the G component select signal Gsel,and the B component select signal Bsel generated by the data line drivercircuit 40 as described above are supplied to the display panel 20, forexample. The demultiplexer DMUX_(L) of the display panel 20 electricallyconnects the data line S_(L) with the R component data line RS_(L) basedon the R component select signal Rsel, whereby the data voltage DP_(L)Rof the operational amplifier circuit OPC_(L) is supplied to the Rcomponent data line RS_(L).

When the count value incremented based on the clock signal CLK coincideswith the G component display start time data (E3), the G componentselect signal Gsel is set at the H level. When the count value coincideswith the G component display end time data (E4), the G component selectsignal Gsel is set at the L level.

A period in which the G component select signal Gsel is set at the Hlevel is the G component select period. In the G component selectperiod, the high-potential-side voltage supply circuit 120 supplies theG component high-potential-side voltage VHG to one end of the resistorcircuit 112 as the high-potential-side voltage VH, and thelow-potential-side voltage supply circuit 130 supplies the G componentlow-potential-side voltage VLG to the other end of the resistor circuit112 as the low-potential-side voltage VL.

In the G component select period, the selector 140 outputs the Gcomponent correction switch control signals c1-1G to c1-4G, . . . ,c62-1G to c62-4G, and c63-1G to c63-4G as the correction switch controlsignals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4.Therefore, in the resistor circuit 112 of the gamma correction resistorcircuit 110, the resistance between the resistive division nodes iscorrected for the G component. Therefore, the reference voltages V0G toV63G gamma-corrected for the G component are output to the referencevoltage select ROM circuits as the reference voltages V0 to V63 throughthe reference voltage signal lines.

For example, the reference voltage select ROM circuit VSEL_(L) among thereference voltage select ROM circuits VSEL₁ to VSEL_(N) selects one ofthe reference voltages V0 to V63 as the data voltage DP_(L)G based onthe G component grayscale data O_(L)D, and the operational amplifiercircuit OPC_(L) drives the data line S_(L) of the display panel 20 basedon the data voltage DP_(L)G. The demultiplexer DMUX_(L) of the displaypanel 20 electrically connects the data line S_(L) with the G componentdata line GS_(L) based on the G component select signal Gsel, wherebythe data voltage DP_(L)G of the operational amplifier circuit OPC_(L) issupplied to the G component data line GS_(L). The same description alsoapplies to the reference voltage select ROM circuits and the operationalamplifier circuits provided corresponding to other data lines.

When the count value incremented based on the clock signal CLK coincideswith the B component display start time data (E5), the B componentselect signal Bsel is set at the H level. When the count value coincideswith the B component display end time data (E6), the B component selectsignal Bsel is set at the L level.

A period in which the B component select signal Bsel is set at the Hlevel is the B component select period. In the B component selectperiod, the high-potential-side voltage supply circuit 120 supplies theB component high-potential-side voltage VHB to one end of the resistorcircuit 112 as the high-potential-side voltage VH, and thelow-potential-side voltage supply circuit 130 supplies the B componentlow-potential-side voltage VLB to the other end of the resistor circuit112 as the low-potential-side voltage VL.

In the B component select period, the selector 140 outputs the Bcomponent correction switch control signals c1-1B to c1-4B, . . . ,c62-1B to c62-4B, and c63-1B to c63-4B as the correction switch controlsignals c1-1 to c1-4, . . . , c62-1 to c62-4, and c63-1 to c63-4.Therefore, in the resistor circuit 112 of the gamma correction resistorcircuit 110, the resistance between the resistive division nodes iscorrected for the B component. Therefore, the reference voltages V0B toV63B gamma-corrected for the B component are output to the referencevoltage select ROM circuits as the reference voltages V0 to V63 throughthe reference voltage signal lines.

For example, the reference voltage select ROM circuit VSEL_(L) among thereference voltage select ROM circuits VSEL_(i) to VSEL_(N) selects oneof the reference voltages V0 to V63 as the data voltage DP_(L)B based onthe B component grayscale data B_(L)D, and the operational amplifiercircuit OPC_(L) drives the data line S_(L) of the display panel 20 basedon the data voltage DP_(L)B. The demultiplexer DMUX_(L) of the displaypanel 20 electrically connects the data line S_(L) with the B componentdata line BS_(L) based on the B component select signal Bsel, wherebythe data voltage DP_(L)B of the operational amplifier circuit OPC_(L) issupplied to the B component data line BS_(L). The same description alsoapplies to the reference voltage select ROM circuits and the operationalamplifier circuits provided corresponding to other data lines.

3. Electronic Instrument

A display device in an embodiment of the present invention is providedas a display section of an electronic instrument. In more detail, thedisplay device may be incorporated into various electronic instrumentssuch as a portable telephone, a portable information instrument (such asPDA), a digital camera, a projector, a portable audio player, a massstorage device, a video camera, an electronic notebook, and a globalpositioning system (GPS).

FIG. 22 is a block diagram showing an example of an electronicinstrument to which the display device in an embodiment of the presentinvention is applied. FIG. 22 shows a portable telephone as an example.

A display device 900 in this embodiment is connected with an MPU 910through a bus. A memory 920 and a communication section 930 are alsoconnected to the bus.

The MPU 910 controls each section through the bus. The memory 920includes a storage region corresponding to each pixel of a display panel902 of the display device 900, and image data randomly written by theMPU 910 is sequentially read along a scan direction.

The communication section 930 performs various types of control forcommunicating with the outside (host device or another electronicinstrument, for example). The function of the communication section 930may be realized by hardware such as various processors or acommunication ASIC, a program, and the like.

In this electronic instrument, the MPU 910 sets an operation mode(information for determining the size of a display image, a horizontalscanning cycle, and a vertical scanning cycle, or the like) of a datadriver 906 and a scan driver 908 in a display controller 904, forexample. The display controller 904 generates various timing signalsnecessary for driving the display panel 902 and supplies the generatedtiming signals to the data driver 906. The data driver 906 has the sameconfiguration as the configuration of the data line driver circuit 40 inthis embodiment. The scan driver 908 has the same configuration as theconfiguration of the scan line driver circuit 30 in this embodiment, andscans scan lines of the display panel 902 based on the display controlfrom the display controller 904.

FIG. 23 is a perspective diagram showing a portable telephone as anexample of an electronic instrument to which the display device in thisembodiment is applied.

A portable telephone 1200 includes a plurality of operation buttons1202, a receiver 1204, a microphone 1206, and a panel 1208. As the panel1208, a display panel which forms the display device in this embodimentis applied. The panel 1208 displays a radio field intensity, numbers,and characters during waiting, and sets the entire area as a displayregion during reception and transmission. In this case, powerconsumption can be reduced by controlling the display region.

Although only some embodiments of the present invention have beendescribed in detail above, those skilled in the art will readilyappreciate that many modifications are possible in the embodimentswithout materially departing from the novel teachings and advantages ofthis invention. Accordingly, all such modifications are intended to beincluded within scope of this invention.

For example, the present invention may be applied not only to drive theabove-described organic EL panel, but also to drive anotherelectroluminescent panel, a liquid crystal device, or a plasma displaydevice.

This embodiment illustrates the case where one pixel is made up of threedots and includes the R component, the G component, and the B component.However, the present invention is not limited thereto. The samedescription also applies to the case where one pixel is made up of twocolor components or one pixel is made up of four or more colorcomponents.

In this embodiment, the function of the demultiplexers DMUX₁ to DMUX_(N)of the display panel may be provided to the data line driver circuit 40.

Part of requirements of any claim of the present invention could beomitted from a dependent claim which depends on that claim. Moreover,part of requirements of any independent claim of the present inventioncould be made to depend on any other independent claim.

What is claimed is:
 1. A voltage generation circuit that generates aplurality of voltages, comprising: a resistor circuit that includes aplurality of resistors, the plurality of resistors being connectedserially, the resistor circuit outputting the plurality of voltages; anda first voltage supply circuit that supplies a first voltage to one endof the resistor circuit, the first voltage being selected among a secondvoltage and a third voltage.
 2. The voltage generation circuit accordingto claim 1, further comprising: a second voltage supply circuit thatsupplies a fourth voltage to the another end of the resistor circuit,the fourth voltage being selected among a fifth voltage and a sixthvoltage.
 3. The voltage generation circuit according to claim 1, furthercomprising: a gamma correction circuit that includes the resistorcircuit, one of the plurality of resistors being a reference voltagecorresponding to a level of grayscale data, the second voltagecorresponding to a first color component of the grayscale data, thethird voltage corresponding to a second color component of the grayscaledata, the gamma correction circuit supplying the reference voltage toone of a plurality of reference voltage signal lines.
 4. The voltagegeneration circuit according to claim 2, further comprising: a gammacorrection circuit that includes the resistor circuit, one of theplurality of resistors being a reference voltage corresponding to alevel of grayscale data, the second voltage and the fifth voltagecorresponding to a first color component of the grayscale data, thethird voltage and the sixth voltage corresponding to a second colorcomponent of the grayscale data, the gamma correction circuit supplyingthe reference voltage to one of a plurality of reference voltage signallines.
 5. A driver, comprising the voltage generation circuit accordingto claim
 1. 6. A display device, comprising the voltage generationcircuit according to claim
 1. 7. An electronic instrument, comprisingthe voltage generation circuit according to claim 1.